Power/performance Advantages of Victim Buuer in High-performance Processors

In this paper, we propose several diierent data cache conngurations and analyze their power as well as performance implications on the processor. Unlike most existing work in low power microprocessor design, we explore a high performance processor with the latest innovations for performance. Using a detailed, architectural-level simulator, we evaluate full system performance using several diierent power/performance sensitive cache conngu-rations. We then use the information obtained from the simulator to calculate the energy consumption of the memory hierarchy of the system. We show that victim buuer ooers improved cache energy consumption over other techniques (10% compared to 3.8%), while at the same time provides comparable performance gains (3.54% compared to 3.45%). In this paper we will concentrate on reducing the energy demands of an ultra high-performance processor, such as the Pentium Pro or the Alpha 21264, which uses superscalar, speculative, out-of-order execution. In particular, we will investigate architectural-level solutions that achieve a power reduction in the memory subsystem of the processor without compromising performance. Prior research has been aimed at measuring and recommending optimal cache conngu-ration for power. In 9], the authors determined that high performance caches were also the lowest power consuming caches since they reduce the traac to the lower level of the memory system. The work by Kin 7] proposed accessing a small lter cache before access-ing the rst level cache to reduce the accesses (and energy consumption) from DL1. The idea lead to a large reduction in memory hierarchy energy consumption, but also resulted in a substantial reduction in processor performance. While this reduction in performance may be tolerable for some applications, the high-end market will not make such a sacriice. This paper will propose memory hierarchy conngurations that reduce power while retaining performance. Reducing cache misses due to line connicts has been shown to be eeective in improving overall system performance in high-performance processors. Techniques to reduce connicts include increasing cache associativity, use of victim caches 5], or cache bypassing with and without the aid of a buuer 4, 8, 10]. Figure 1 shows the design of the memory hierarchy when using a buuer alongside the rst level data cache. Also included in the